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Micrel, Inc.
3.3V, 500MHz, 1:9 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/ TRANSLATOR
Precision Edge(R) SY89808L Precision Edge(R)
SY89808L
FEATURES
s 9 differential HSTL (1.5V compatible) output pairs s 500MHz maximum clock frequency s Triple-buffered enable function s 3.3V core supply, 1.8V output supply for reduced s s s s s
Precision Edge(R)
DESCRIPTION
The SY89808L is a High-Performance Bus Clock Driver with 9 differential HSTL (High-Speed Transceiver Logic) 1.5V compatible output pairs. The part is designed for use in lowvoltage (3.3V/1.8V) applications which require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the CLK_SEL pin. The Output Enable (OE) is synchronous and triple-buffered so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any potential of generating a runt clock pulse when the device is enabled/disabled, as can occur with an asynchronous control. The triple-buffering feature provides a three-clock delay from the time the OE input is asserted/de-asserted to when the clock appears at the outputs. The SY89808L features an ultra-low pin-to-pin skew of less than 25ps. The SY89808L is available in a 32-TQFP space saving package, enabling a lower overall cost solution.
power LVPECL and HSTL inputs HSTL outputs drive 50 to ground with no offset voltage Low pin-to-pin skew (25ps max.) Guaranteed over industrial -40C to +85C temperature range Available in 32-pin TQFP package
APPLICATIONS
s Workstations s Parallel processor-based systems s High-performance computing s Communications
TRUTH TABLE
OE(1) CLK_SEL 0 1 0 1
LOGIC SYMBOL
CLK_SEL HSTL_CLK /HSTL_CLK 0 9 9 LVPECL_CLK 1 /LVPECL_CLK
EN ENABLE LOGIC
Q0 - Q8 LOW LOW HSTL_CLK LVPECL_CLK
/Q0 - /Q8 HIGH HIGH /HSTL_CLK /LVPECL_CLK
0 0 1 1
Q0 -- Q8 /Q0 -- /Q8
Notes: 1. The OE (output enable) signal is synchronized with the low level of the HSTL_CLK and LVPECL_CLK signal.
TYPICAL PERFORMANCE
Output Amplitude vs. Frequency
OE
900 800
AMPLITUDE (mV)
700 600 500 400 300
1000 1200 1400 1600
Rev.: E
0
200
400
600
Precision Edge is a registered trademark of Micrel, Inc. M9999-091405 hbwhelp@micrel.com or (408) 955-1690
FREQUENCY (MHz)
Amendment: /0
1
800
200
Issue Date: September 2005
Micrel, Inc.
Precision Edge(R) SY89808L
PACKAGE/ORDERING INFORMATION
VCCO VCCO /Q0 /Q1 /Q2
Ordering Information(1)
Part Number
VCCO Q3 /Q3 Q4 /Q4 Q5 /Q5 VCCO
Q0
Q1
Q2
VCCI HSTL_CLK /HSTL_CLK CLK_SEL LVPECL_CLK /LVPECL_CLK GND OE
32 31 30 29 28 27 26 25 24 1 2 3 4 5 6 7 8 23 22
Package Operating Type Range T32-1 T32-1 T32-1 T32-1 Industrial Industrial Industrial Industrial
Package Marking SY89808LTI SY89808LTI
Lead Finish Sn-Pb Sn-Pb
SY89808LTI SY89808LTITR(2) SY89808LTG(3) SY89808LTGTR(2, 3)
Top View
21 20 19 18
SY89808LTG with NiPdAu Pb-Free bar line indicator Pb-Free SY89808LTG with NiPdAu Pb-Free bar line indicator Pb-Free
17 9 10 11 12 13 14 15 16
/Q8 /Q7 /Q6 VCCO VCCO Q8 Q7 Q6
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs.
32-Pin TQFP (T32-1)
PIN DESCRIPTION
Pin Number 2, 3 Pin Name HSTL_CLK, /HSTL_CLK LVPECL_CLK, /LVPECL_CLK CLK_SEL OE Type HSTL Input LVPECL Input LVTTL Input LVTTL Input Pin Function Differential clock input selected by CLK_SEL. Can be left floating if not selected. Floating input, if selected produces an indeterminate output. HSTL input signal requires external termination 50 to GND. Differential clock input selected by CLK_SEL. Can be left floating. Floating input, if selected produces a LOW at the output (internal 75 pull-downs). Requires external termination. 75k pull-up. Selects HSTL_CLK input when LOW and LVPECL_CLK output when HIGH. 11k pull-up. Enable input synchronized internally to prevent glitching of the Q0-Q8 and /Q0-/Q8 outputs. Must be a minimum of three clock periods wide if synchronous with the CLK inputs and must meet the tS and tH requirements (refer to AC Electrical Characteristics). If asynchronous, must be a minimum of four clock periods wide. 11k pull-up. Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated with 50 to GND. Q0-Q8 outputs are static LOW when OE = LOW. Unused output pairs may be left floating. Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated with 50 to GND. /Q0-/Q8 outputs are static HIGH when OE = LOW. Unused output pairs may be left floating. Core VCC connected to 3.3V supply. Bypass with 0.1F in parallel with 0.01F low ESR capacitors as close to VCCI pin as possible. Output Buffer VCC connected to 1.8V supply. Bypass with 0.1F in parallel with 0.01F low ESR capacitors as close to VCCO pins as possible. All VCCO pins should be connected together on the PCB. Ground.
5, 6
4 8
31, 29, 27, 23, 21, 19, 15, 13, 11 30, 28, 26, 22, 20, 18, 14, 12, 10 1 9, 16, 17, 24, 25, 32 7
Q0-Q8
HSTL Output
/Q0-/Q8
HSTL Output
VCCI VCCO
VCC Core Power VCC Output Power Ground
GND
M9999-091405 hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge(R) SY89808L
Absolute Maximum Ratings(1)
Supply Voltage (VIN) ..................................... -0.5V to VCCI VCC Pin Potential to Ground Pin (VCCI, VCCO) ............................................ -0.5V to +4.0V DC Output Current, Output HIGH (IOUT) .................. -50mA Lead Temperature (soldering, 20 sec.) ..................... 260C Storage Temperature (TS) ....................... -65C to +150C
Operating Ratings(2)
Supply Voltage (VCCI) ............................................... +3.15V to +3.45V (VCCO) ................................................. +1.6V to +2.0V Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance TQFP (JA) -Still-Air ........................................................... 50C/W -500lfpm .......................................................... 42C/W TQFP (JC) .......................................................... 20C/W
DC ELECTRICAL CHARACTERISTICS
Power Supply TA = -40C to +85C, unless otherwise stated. Symbol VCCI VCCO ICCI Parameter VCC Core VCC Output ICC Core Max VCC, No Load Condition Min 3.15 1.6 -- Typ 3.3 1.8 80 Max 3.45 2.0 110 Units V V mA
HSTL VCCI = 3.3V 5%; VCCO = 1.8V 10%; RL = 50 to GND; TA = -40C to +85C, unless otherwise stated. Symbol VOH VOL VIH VIL VX IIH IIL Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Crossover Voltage Input HIGH Current Input LOW Current Condition Min 1.0 0.2 VX +0.1 -0.3 0.68 +20 -- Typ -- -- -- -- -- -- -- Max 1.2 0.4 1.6 VX -0.1 0.9 -350 -500 Units V V V V V A A
LVPECL VCCI = 3.3V 5%; VCCO = 1.8V 10%; TA = -40C to +85C, unless otherwise stated. Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Condition Min Max Units V V A A VCCI - 1.165 VCCI - 0.880 VCCI - 1.810 VCCI - 1.475 -- 0.5 +150 --
LVCMOS/LVTTL VCCI = 3.3V 5%; VCCO = 1.8V 10%; TA = -40C to +85C, unless otherwise stated. Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Condition Min 2.0 -- +20 -- Typ -- -- -- -- Max -- 0.8 -250 -600 Units V V A A
Notes: 1. Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. M9999-091405 hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge(R) SY89808L
AC ELECTRICAL CHARACTERISTICS
VCCI = 3.3V 5%; VCCO = 1.8V 10%; All outputs are loaded with 50 to GND; TA = -40C to +85C, unless otherwise stated. Symbol fMAX tpd tSKEW tSKPP Vpp VCMR tS tH t r , tf tJITTER Parameter Maximum Operating Frequency Propagation Delay CLK-to-Q SEL-to-Q Within-Device Skew Part-to-Part Skew Minimum Input Swing LVPECL_CLK Common Mode Range LVPECL_CLK OE Set-Up Time OE Hold Time Output Rise/Fall Time (20% - 80%) Cycle-to-Cycle Jitter Total Jitter Note 9 Note 10 Condition VOUT 450mV Note 3 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Min 500 0.800 0.800 -- -- 150 -1.5 1.0 0.5 250 Typ -- 1.000 1.200 -- -- -- -- -- -- 450 Max -- 1.200 1.700 25 400 -- -0.4 -- -- 650 1 10 Units MHz ns ns ps ps mV V ns ns ps psRMS psPP
3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. 4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. 5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. 6. The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. 7. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.). The lower end of the CMR range varies 1:1 with VCCI. The VCMR (min) will be fixed at 3.3V - |VCMR (min)|. 8. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock. 9. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn-Tn-1 where T is the time between rising edges of the output signal. 10. Total jitter definition: with an ideal clock source of fmax, no more than one output edge in 1012 output edges will deviate by more than the specified amount.
M9999-091405 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89808L
TIMING DIAGRAMS
Assert Latency CLK
De-assert Latency
tS OE
tH
Q0 - Q8
Notes: 1. The OE input signal must be a minimum of 3 clock periods with width. 2. The internal enable is asserted and de-asserted on the falling edge of clock. 3. The internal enable occurs 2.5 clock cycles (plus the set-up time of OE with the rising edge of clock) after the rising edge of the external OE. 4. If OE does not meet the tS of tH specifications as in asynchronous applications, OE must be a minimum of 4 clock periods in width.
HSTL_CLK, LVPECL_CLK /HSTL_CLK, /LVPECL_CLK tPD Q0 - Q8 /Q0 - /Q8
CLK_SEL tPD Q0 - Q8 /Q0 - /Q8 tPD
M9999-091405 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89808L
TYPICAL OPERATING CHARACTERISTICS
VCCI = 3.0V, VCCO = 1.8V, TA = 25C, unless otherwise stated.
200MHz Output
/Q /Q
400MHz Output
Output Swing (100mV/div.)
Output Swing (100mV/div.)
Q Q
TIME (700ps/div)
TIME (300ps/div)
500MHz Output
Q
Output Swing (100mV/div.)
/Q
TIME (300ps/div)
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Micrel, Inc.
Precision Edge(R) SY89808L
LVPECL/HSTL INPUTS
VCC VCC
LVPECL_CLK 75k 75k
HSTL_CLK /HSTL_CLK Clamp
/LVPECL_CLK
GND
GND
Figure 1. Simplified LVPECL Input Stage
Figure 2. Simplified HSTL Input Stage
HSTL OUTPUTS
QOUT 1.6V QOUT -- /QOUT
800mV /QOUT
QOUT
/QOUT
Figure 3. Output Driver Signal Levels (Single-Ended)
Figure 4. Output Driver Signal Levels (Differential)
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number SY89809L SY89823L Function 3.3V 1:9 High-Performance, Low-Voltage Bus Clock Driver 3.3V, 500MHz 1:22 Differential HSTL (1.5V) Fanout Buffer/Translator Exposed Pad Application Note HBW Solutions MIC3775 New Products and Applications 750mA Cap Low-Voltage Low-Dropout Regulator Data Sheet Link www.micrel.com/product-info/products/sy89809l.shtml www.micrel.com/product-info/products/sy89823l.html www.amkor.com/products/notes_papers/epad.pdf www.micrel.com/product-info/products/solutions.shtml www.micrel.com/product-info/products/mic3775.shtml
M9999-091405 hbwhelp@micrel.com or (408) 955-1690
7
Micrel, Inc.
Precision Edge(R) SY89808L
32 LEAD TQFP (T32-1)
Package Notes: Package meets Level 2 qualification.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-091405 hbwhelp@micrel.com or (408) 955-1690
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